This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-134401, filed May 14, 1999; and No. 11-375404, filed Dec. 28, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device incorporating a semiconductor epitaxial substrate and a method of manufacturing the same. More particular, the present invention relates to a semiconductor epitaxial substrate incorporating an epitaxial layer formed on a semiconductor substrate through mediation of a native oxide film and a method of manufacturing the same. More particular, the present invention relates to a method of manufacturing a semiconductor device incorporating a MOS transistor formed by using an elevated source/drain technology for forming an epitaxial layer on a source/drain impurity diffused region by using selective epitaxial growth formed through mediation of a native oxide film, and a semiconductor device incorporating a SALICIDE (Self-Aligned Silicide) MOS transistor formed by using the manufacturing method.
Since devices for constituting an LSI have been shrinked, problems have been increased which exert influences on the performance of the LSI. The problems are exemplified by a short-channel effect of a MOS transistor element and increase of the parasitic capacitance. To solve the problems, a SOI (Silicon on Insulator) structure has been investigated.
The SOI structure encounters a problem in that the crystallinity of a channel region cannot easily be maintained. Therefore, at least a wafer bonding technology or SIMOX (Separation by Implanted Oxygen) technology must be used. The foregoing technologies cause the cost increase of material and decrease of manufacturing yield to occur. The foregoing technologies encounter considerably increase of the cost as compared with the conventional technology which uses CZ (Czochralski) substrate.
To obtain high electron mobility in the channel region, an attempt has been made such that a SiGe mixed crystal layer is formed on a silicon substrate so as to be used as the channel region. In the foregoing case, a silicon substrate must be used as the substrate because substrates having high quality are easily available.
To obtain high electron mobility, it is preferable that the mixing ratio of Ge is raised. Since the lattice constant of Si and that of Ge are different from each other, a high-quality epitaxial substrate free from the defects cannot be obtained when the Ge mixing ratio is 20% or higher.
To expand the range of the possibilities of the LSI structure, an attempt has been made such that a silicon epitaxial growth step is inserted into a process for manufacturing the semiconductor device. For example, a semiconductor device is formed, and then the silicon epitaxial growth is performed on the device. Thus, formation of the device is again performed so that multi-layered semiconductor device formation is permitted. As a result, the device formation density can considerably be raised.
To achieve the foregoing technology, a defect free silicon epitaxial layer must be formed. Therefore, it has been considered very important to sufficiently remove a native oxide film on the silicon substrate which obstructs the growth process before the silicon epitaxial growth is performed.
If impurities, such as oxygen, are present on the substrate even in a small quantity, defects, such as dislocations, generate in the silicon epitaxial layer starting with surface oxide. To remove surface oxide, a deoxidizing heat treatment must be performed in a high temperature region near 1000xc2x0 C. Therefore, the formation process of the high-quality silicon epitaxial layer cannot easily be employed in the device employed, silicidation occurs between metal and the silicon substrate. Thus, deposited metal reacts with the silicon substrate, causing silicidation proceeds while the surface layer of the silicon substrate is being eroded.
Therefore, formation of the shallow SID region in the silicon substrate and formation of a shallow junction free from large leakage current between the silicon substrate and the SID region have been very difficult.
To solve the above-mentioned problem, employment of a method has been considered with which silicon single crystal is epitaxially grown on the SID region formed on the silicon substrate. Then, the SID region of the MOS transistor is elevated to be higher than the surface of the silicon substrate, and then metal is deposited. Then, silicidation is allowed to proceed.
The foregoing method is able to simultaneously meet both of the requirement for forming a low-resistance SID region required to maintain the high-speed operation of the MOS transistor and the requirement for forming a shallow junction in the lower portion of the surface of the silicon substrate. The structure of the MOS transistor formed by epitaxially growing silicon on the SID region formed on the silicon substrate is called an elevated SID structure.
Usually, the elevated SID structure is formed by manufacturing process, the processing temperature of which has an upper limit.
Since the operation speed of the MOS transistor has been raised and the structure of the same has been shrinked, a shallow source/drain impurity diffusion region (hereinafter called a SID region) of the MOS transistor has been required which has low resistance.
A high-performance transistor must have shallow junctions in the SID region. When a silicon layer is epitaxially grown on the SID region and implanting impurity ions upon the silicon epitaxial layer, shallow junctions can be formed from the surface of the silicon substrate. As described above, employment of the silicon epitaxial growth in the process for manufacturing the MOS LSI has become important in recent years.
In the conventional MOS LSI industrial field, there is a technology called a self-aligned silicide or SALICIDE for realizing a shrinked device which is capable of performing a high-speed operation. That is, metal, such as Co or Ti, is deposited in an impurity diffused region in a self-aligned manner to form silicide.
On the other hand, progress of the technology for shrinking semiconductor device raises a necessity for shallow SID diffused region in order to prevent the short channel effect. When the SALICIDE technology is performing heat treatment at 800xc2x0 C. or higher by operating a LPCVD (Low Pressure Chemical Vapor Deposition) reactor. Therefore, the impurity profiles in the S/D region and the channel region, which has been formed by ion implantation, are changed. Thus, the designed performance cannot be exhibited.
Since B (boron) in the gate electrode is diffused into the channel region, the gate electrode is depleted, a critical problem arises in that the threshold voltage is changed.
To perform selective epitaxial growth, an UHVCVD (Ultra High Vacuum Chemical Vapor Deposition) reactor or the LPCVD reactor is usually used. In particular, it is preferable that the LPCVD reactor is used because the LPCVD reactor has frequently been employed in the ULSI manufacturing process and has an excellent track record from viewpoints of improving the manufacturing efficiency and the stability of the process.
A representative selective epitaxial growth using the LPCVD method is performed by a vapor phase epitaxial growth in a mixed atmosphere of a silicon source material, such as silane or dichlorosilane and etching gas of chlorine or hydrochloric acid.
Since thermal diffusion of dopants is tightly limited in the future shrinked semiconductor device, it is preferable that the thermal process of the CVD is performed at lower temperatures.
To obtain a practically satisfactory deposited film thickness by the vapor phase growth method using the LPCVD, high temperature heat treatment at 800xc2x0 C. or higher is required. In the next generation device that has the gate length of 0.1 xcexcm or shorter, change in the channel profile and diffusion of impurities from the gate to the channel cannot be ignored.
As described above, employment of the SOI (Silicon on Insulator) structure has been expected to be adaptable to the shrinking of the devices constituting the MOS LSI. An SOI structure having excellent crystallinity in the channel region cannot easily be realized. Therefore, at least the wafer bonding technology and the SIMOX technology must be employed. The foregoing technologies, however, encounter increase in the number of manufacturing steps, the cost increase of the material and lowering in the manufacturing yield. As compared with the conventional technology using the CZ substrate, the cost cannot be reduced.
To obtain high electron mobility in the channel region, an attempt has been made that a SiGe Layer is formed on the silicon substrate. There arises a problem in that a high-quality epitaxial layer exhibiting a low defect density cannot be obtained when the Ge mixed crystal ratio is 20% or higher due to the large difference between the lattice constant of Si and that of Ge.
When a silicon epitaxial step is employed in the process for manufacturing a semiconductor device to expand the range of the possibilities of the LSI structure, a high-temperature heat treatment at about 1000xc2x0 C. is required to obtain a silicon epitaxial layer exhibiting excellent crystallinity. Thus, there arises a problem in that the high-temperature heat treatment should be included in the device manufacturing process, the process temperature of which is highly limited.
To form a shallow S/D junction suitable for a shrinked MOS transistor by the SALICIDE technology, employment of an elevated S/D structure raises a necessity for performing a high-temperature step at 800xc2x0 C. or higher by using an LPCVD reactor. The channel region formed previously and the impurity profile in the S/D region are undesirably changed. Thus, there arises a problem in that a designed performance of the MOS transistor cannot be obtained.
To solve the above-mentioned problems, a first object of the present invention is to provide a high-quality epitaxial silicon substrate formed by using a method of changing an amorphous silicon layer deposited in a low-temperature region into single crystal by a solid phase epitaxial growth method, a semiconductor substrate incorporating a SOI structure such as SIMOX by applying the epitaxial silicon substrate, and a high-quality silicon epitaxial substrate in which the mixed crystal ratio of Ge is higher than 20% and capable of reducing crystal defects and a manufacturing method therefor.
A second object of the present invention is to raise the density and the performance of a semiconductor device by forming a MOS transistor having an elevated S/D structure and a SALICIDE structure by employing a growth step of an epitaxial silicon single crystal layer in a process for manufacturing a semiconductor device such that the increase in the number of manufacturing steps, the cost of the material and lowering in the manufacturing yield are prevented.
The present invention relates to a semiconductor device incorporating a semiconductor epitaxial substrate and a manufacturing method therefor. More particularly, an object of the present invention is to provide a semiconductor epitaxial substrate incorporating a high-quality epitaxial single crystal layer formed by depositing an amorphous silicon layer or a polysilicon layer on a semiconductor substrate through mediation of a native oxide film thinner than a mono-molecular layer by vapor phase growth and by forming the layers into a single crystal layer by a solid phase epitaxial growth method (hereinafter called SPE) in a low-temperature region and a manufacturing method therefor.
In the present invention, an amorphous silicon layer or a polysilicon layer is deposited on the overall surface of a silicon substrate including a S/D region of a MOS transistor formed on the silicon substrate. Then, an SPE method is employed to selectively grow single crystal on only the S/D region without any high-temperature process.
The SPE method is able to epitaxially grow single crystal on a silicon substrate by performing only a heat treatment step in a low-temperature region. Therefore, the residual amorphous or polysilicon layer on the surface of the silicon substrate except for the S/D region is removed by etching. Thus, a semiconductor device having an elevated S/D structure can be provided without a necessity for performing a complicated step.
Specifically, a method of manufacturing an epitaxial semiconductor substrate according to the present invention comprises the steps of: forming a thin oxide layer on a semiconductor substrate; depositing either of an amorphous silicon layer or a polysilicon layer on the semiconductor substrate through mediation of the thin oxide layer; and forming an epitaxial semiconductor layer by crystallizing the amorphous silicon layer or the polysilicon layer, wherein
the thickness of the thin oxide layer is in a range from 2xc3x971014 cmxe2x88x922 to 8xc3x971014 cmxe2x88x922 which is a value of a concentration of interface oxide between the semiconductor substrate and the epitaxial semiconductor layer.
A method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming an insulating film embedded in an isolation trench; forming a gate insulating film on a semiconductor substrate; forming a gate electrode covered with an insulating film on the gate insulating film; forming an exposed portion of the surface of the semiconductor substrate by removing the gate insulating film except for at least a lower portion of the gate electrode; forming a thin oxide layer on the surface of the exposed portion of the semiconductor substrate such that the value of the concentration of surface oxide is in a range from 3xc3x971011 cmxe2x88x922 to 1.1xc3x971015 cmxe2x88x922;
depositing an amorphous silicon layer or a polysilicon layer to cover the thin oxide layer which is in contact with the exposed portion of the semiconductor substrate and the gate electrode covered with the insulating film; forming only either the amorphous silicon layer or the polysilicon layer which is in contact with the exposed portion of the semiconductor substrate through mediation of the thin oxide layer into single crystal by selectively solid phase growing either of the amorphous silicon layer or the polysilicon layer; and performing etching to remove either of the amorphous silicon layer or the polycrystalline silicon layer left on the insulating film which covers the gate electrode and the insulating film embedded in the isolation trench.
An epitaxial substrate according to the present invention comprises: a thin oxide layer formed on a semiconductor substrate; and an epitaxial semiconductor layer formed through mediation of the thin oxide layer, wherein a thickness of the thin oxide layer is in a range from 2xc3x971014 cmxe2x88x922 to 8xc3x971014 cmxe2x88x922 which is a value of a concentration of interface oxide between the semiconductor substrate and the epitaxial semiconductor layer.
A semiconductor device according to the present invention comprises: a gate insulating film formed on a semiconductor substrate; a gate electrode covered with an insulating film and formed on the gate insulating film; an exposed surface of the semiconductor substrate formed in a source region and a drain region; a thin oxide layer which is in contact with the exposed surface of the semiconductor substrate; a single crystal layer formed to be in contact with the exposed surface of the semiconductor substrate through mediation of the thin oxide layer such that a thickness of the single crystal layer at an end of the insulating film for covering the gate electrode is the same or larger than the thickness of an other portion of the single crystal layer; a metal silicide layer formed at least on the single crystal layer.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.